Electrically alterable non-volatile memory device
January 3, 2006. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.Patent ReferencesElectrically programmable and erasable memory cell Electrically erasable programmable read only memory Electrically alterable, nonvolatile floating gate memory device Non-volatile static random-access memory cell Semiconductor device having insulated gate type non-volatile semiconductor memory elements Nonvolatile latch Nonvolatile semiconductor memory device with electrically selectable, erasable and programmable function Non-volatile dynamic RAM cell Improved nonvolatile memory circuit using a dual node floating gate memory cell Patent #: 4685083 InventorsAssigneeApplicationNo. 06/815869 filed on 01/03/1986US Classes:365/185.28, Tunnel programming257/318, Additional control electrode is doped region in semiconductor substrate257/319, Plural additional contacted control electrodes257/321, With thin insulator region for charging or discharging floating electrode by quantum mechanical tunneling257/E29.304, Charging by tunneling of carriers (e.g., Fowler-Nordheim tunneling) (EPO)365/185.09, Error correction (e.g., redundancy, endurance)365/185.1, Extended floating gate365/185.21Sensing circuitry (e.g., current mirror)ExaminersPrimary: Clawson, Joseph E. Jr.Attorney, Agent or FirmInternational ClassesH01L 29/66 (20060101)H01L 29/788 (20060101) AbstractIn this invention, an Electrically Alterable Non-Volatile Memory (EANOM) cell is disclosed. The EANOM ceil comprises an MOS transistor, having a source, a gate and a drain. The EANOM cell also has a two-terminal tunnel device, one end of which is connected to the gate of the MOS transistor. The other terminal being labelled "T". The tunnel device causes charges to be stored or removed from the gate of the MOS transistor. In a preferred embodiment, a four-terminal EANOM cell is disclosed. The four terminals of the EANOM cell are terminals T, S (source of the MOS transistor), D (drain of the MOS transistor) and a terminal C which is capacitively coupled to the gate of the MOS transistor. The EANOM cell can be used in a memory circuit to increase the reliability thereof. Two or more EANOM cells are connected in tandem and operate simultaneously. Catastrophic failure of one EANOM cell results in an open circuit with the other EANOM cell continuing to function. | |
