Method of fabrication of MOS transistors having electrodes of metallic silicide
Patent 4780429 Issued on October 25, 1988. Estimated Expiration Date: 
January 12, 2007. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.
January 12, 2007. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.Patent ReferencesSemiconductor planarization process and structures made thereby Method for making planar FET having gate, source and drain in the same plane Manufacturing MOS semiconductor device with planarized conductive layer Patent #: 4713356 InventorsAssigneeApplicationNo. 07/010979 filed on 01/12/1987US Classes:438/237, Including diode257/768, Refractory or platinum group metal or alloy or silicide thereof257/E21.425, With source or drain region formed by Schottky barrier or conductor-insulator-semiconductor structure (EPO)257/E21.433, Where the source and drain or source and drain extensions are self-aligned to sides of gate (EPO)257/E21.507, Formation of contacts to semiconductor by use of metal layers separated by insulating layers, e.g., self-aligned contacts to source/drain or emitter/base (EPO)257/E21.583, Planarization; smoothing (EPO)257/E29.144, On Group III-V material (EPO)257/E29.152, With lateral structure (e.g., poly-silicon gate with lateral doping variation or with lateral composition variation or characterized by sidewalls being composed of conductive, resistivity) (EPO)257/E29.161, Silicide (EPO)438/297, Recessed oxide formed by localized oxidation (i.e., LOCOS)438/583, Silicide438/586, Combined with formation of ohmic contact to semiconductor region438/595Having sidewall structureExaminersPrimary: Hearn, Brian E.Assistant: McAndrews, Kevin Attorney, Agent or FirmInternational ClassesH01L 21/336 (20060101)H01L 21/768 (20060101) H01L 21/02 (20060101) H01L 21/70 (20060101) H01L 21/60 (20060101) H01L 29/40 (20060101) H01L 29/49 (20060101) H01L 29/45 (20060101) Foreign Application Priority Data1985-05-21 FRAbstractIn a method of fabrication of field-effect transistors having very small dimensions, the gate electrode is formed by a first layer of metallic silicide. Insulating embankments are formed along the lateral edges of the gate and a second layer of metallic silicide is then deposited so as to form the source and drain electrodes. At locations in which the second layer covers the first, planning by planarizing etching is performed so as to produce a structure of flat electrodes in which the gate is separated from the source and drain electrodes by a smaller interval than would be possible in the case of separation by photoetching.Other References
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