Process for fabricating electrically alterable floating gate memory devices
Patent 4780424 Issued on October 25, 1988. Estimated Expiration Date: 
September 28, 2007. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.
September 28, 2007. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.Patent ReferencesMOS Devices having buried terminal zones under local oxide regions High density electrically programmable ROM Process for forming complementary integrated circuit devices Semiconductor memory device High density, electrically erasable, floating gate memory cell Patent #: 4561004 InventorsApplicationNo. 07/101642 filed on 09/28/1987US Classes:438/262, Including elongated source or drain region disposed under thick oxide regions (e.g., buried or diffused bitline, etc.)257/316, With additional contacted control electrode257/E21.682, With source and drain on same level and without cell select transistor (EPO)257/E27.103, Electrically programmable ROM (EPO)438/263, Tunneling insulator438/307Using same conductivity-type dopantExaminersPrimary: Chaudhuri, OlikAttorney, Agent or FirmInternational ClassesH01L 21/70 (20060101)H01L 27/115 (20060101) H01L 21/8247 (20060101) AbstractA process for fabricating contactless electrically programmable and electrically erasable memory cells of the flash EPROM type. The contactless cells use elongated source and drain regions disposed beneath field oxide regions. The drain regions are shallow compared to the source regions. The source regions have more graded junctions. Floating gates are formed over a tunnel oxide (120 Å thick) between the source and drain regions with word lines being disposed perpendicular to the source and drain regions. One dimension of the floating gates is formed after the word lines have been patterned by etching the first layer of polysilicon in alignment with the word lines. | |
