Process for manufacturing a monolithic integrated circuit comprising at least one bipolar planar transistor
March 20, 2007. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.Patent ReferencesMethod of manufacturing a semiconductor integrated circuit BI-MOS device Process for manufacturing a monolithic integrated solid-state circuit comprising at least one bipolar planar transistor Method for manufacturing bipolar planar transistors Method for manufacturing fast bipolar transistors Process for manufacturing a monolithic integrated solid-state circuit having at least one insulated-gate field-effect transistor and at least one bipolar transistor Bipolar transistors having vertically arrayed collector-base-emitter with novel polycrystalline base electrode surrounding island emitter and method of making same Fabrication methods for high performance lateral bipolar transistors Monolithic integrated circuit Fabrication methods for high performance lateral bipolar transistors Method of forming bipolar transistors with graft base regions InventorAssigneeApplicationNo. 07/028472 filed on 03/20/1987US Classes:438/234, Including bipolar transistor (i.e., BiMOS)257/370, Combined with bipolar transistor257/509, Combined with pn junction isolation (e.g., isoplanar, LOCOS)257/E21.033, Comprising inorganic layer (EPO)257/E21.375, Silicon vertical transistor (EPO)257/E21.507, Formation of contacts to semiconductor by use of metal layers separated by insulating layers, e.g., self-aligned contacts to source/drain or emitter/base (EPO)257/E21.696, Bipolar and MOS technologies (EPO)438/207, Including isolation structure438/362, Recessed oxide by localized oxidation (i.e., LOCOS)438/365, Forming active region from adjacent doped polycrystalline or amorphous semiconductor438/370Forming buried region (e.g., implanting through insulating layer, etc.)ExaminersPrimary: Hearn, Brian E.Assistant: Wilczewski, Mary Attorney, Agent or FirmInternational ClassesH01L 21/033 (20060101)H01L 21/02 (20060101) H01L 21/70 (20060101) H01L 21/60 (20060101) H01L 21/331 (20060101) H01L 21/8249 (20060101) Foreign Application Priority Data1986-03-22 EPAbstractThe invention includes a method of manufacture of monolithic integrated VLSI circuits comprising bipolar transistors whose base regions are contacted in a self-aligned manner in proximity to the respective emitter regions by the use of silicide layers. The invention starts out from a process which, when using an insulating masking layer portion covering up the emitter area of the planar transistor, permits the self-aligned fabrication of emitter regions extending to the adjoining base region and to the base contacting region. Further embodiments of the process according to the invention permit the simultaneous manufacture of co-integrated CMOS circuits and of polycrystalline. Si-conductor leads whose resistances are reduced owing to the use of silicide layers. | |
