Apparatus and method for prefetching subblocks from a low speed memory to a high speed memory of a memory hierarchy depending upon state of replacing bit in the low speed memory
Patent 4774654 Issued on September 27, 1988. Estimated Expiration Date: 
September 27, 2005. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.
September 27, 2005. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.Patent References 3928857 Cache memory organization utilizing miss information holding registers to prevent lockup from cache misses Cache/disk subsystem with dual aging of cache entries Second level cache replacement method and apparatus I/O Storage controller cache system with prefetch determined by requested record's position within data block Method and system for handling sequential data in a hierarchical store Patent #: 4533995 InventorsApplicationNo. 06/685527 filed on 12/24/1984US Classes:711/122, Hierarchical caches711/118CachingExaminersPrimary: Zache, Raulfe B.Assistant: Lee, Thomas C. Attorney, Agent or FirmInternational ClassG06F 12/08 (20060101)AbstractA prefetching mechanism for a memory hierarchy which includes at least two levels of storage, with L1 being a high-speed low-capacity memory, and L2 being a low-speed high-capacity memory, with the units of L2 and L1 being blocks and sub-blocks respectively, with each block containing several sub-blocks in consecutive addresses. Each sub-block is provided an additional bit, called a r-bit, which indicates that the sub-block has been previously stored in L1 when the bit is 1, and has not been previously stored in L1 when the bit is 0. Initially when a block is loaded into L2 each of the r-bits in the sub-block are set to 0. When a sub-block is transferred from L1 to L2, its r-bit is then set to 1 in the L2 block, to indicate its previous storage in L1. When the CPU references a given sub-block which is not present in L1, and has to be fetched from L2 to L1, the remaining sub-blocks in this block having r-bits set to 1 are prefetched to L1. This prefetching of the other sub-blocks having r-bits set to 1 results in a more efficient utilization of the L1 storage capacity and results in a highter hit ratio. | |
