Method of making symmetrically controlled implanted regions using rotational angle of the substrate
June 12, 2007. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.Patent ReferencesMethod of making direct metal contact to buried layer Masking technique usable in manufacturing semiconductor devices Method of making a MESFET having same type conductivity for source, drain, and gate regions Simultaneously forming fully implanted DMOS together with enhancement and depletion mode MOSFET devices Method of making a high voltage V-groove solar cell Method of manufacturing Schottky field-effect transistors utilizing shadow masking Method of exposure of chemically machineable light-sensitive glass Ion implanting method Method for exposure of chemically machinable light-sensitive glass Method of making extremely small area PNP lateral transistor by angled implant of deep trenches followed by refilling the same with dielectrics InventorsAssigneeApplicationNo. 07/061264 filed on 06/12/1987US Classes:438/286, Asymmetric257/344, With lightly doped portion of drain region adjacent channel (e.g., LDD structure)257/408, Including lightly doped drain portion adjacent channel (e.g., lightly doped drain, LDD device)257/E21.345, Characterized by the angle between the ion beam and the crystal planes or the main crystal surface (EPO)257/E21.433, Where the source and drain or source and drain extensions are self-aligned to sides of gate (EPO)257/E29.04, Of field-effect transistors with insulated gate (EPO)257/E29.063, With inactive supplementary region (e.g., for preventing punch-through, improving capacity effect or leakage current) (EPO)257/E29.255, With field effect produced by insulated gate (EPO)257/E29.27, With buried channel (EPO)438/289, Doping of semiconductive channel region beneath gate insulator (e.g., adjusting threshold voltage, etc.)438/302Oblique implantationExaminersPrimary: Roy, III, UpendraAttorney, Agent or FirmInternational ClassesH01L 21/265 (20060101)H01L 21/336 (20060101) H01L 21/02 (20060101) H01L 29/02 (20060101) H01L 29/78 (20060101) H01L 29/66 (20060101) H01L 29/08 (20060101) H01L 29/10 (20060101) Foreign Application Priority Data1986-06-13 JPAbstractA method of fabricating a field effect transistor, wherein impurity diffusion layers of source and drain are formed by an ion implantation method using the gate electrode as the mask by inclining the semiconductor substrate with respect to the ion beam incident direction so as to prevent the channeling effect and also rotating it in planarity with respect to the ion beam scanning plane. As a result, impurity diffusion layers can be formed symmetrically with respect to the gate electrode. | |
