Programmable logic array
Patent 4766569 Issued on August 23, 1988. Estimated Expiration Date: 
June 5, 2006. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.
June 5, 2006. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.Patent ReferencesIntegrated programmable logic arrangement User reprogrammable programmed logic array A.C. Testing of logic arrays Programmable array logic circuit with testing and verification circuitry Detector of predetermined patterns of encoded data signals Patent #: 4631695 InventorsAssigneeApplicationNo. 06/871063 filed on 06/05/1986US Classes:365/185.11, Bank or block architecture326/44, Field effect transistor340/14.3, Programmable365/185.21, Sensing circuitry (e.g., current mirror)365/185.22, Verify signal365/201, Testing714/725Programmable logic array (PLA) testingExaminersPrimary: Popek, Joseph A.Attorney, Agent or FirmInternational ClassesH03K 19/177 (20060101)G01R 31/28 (20060101) G01R 31/3185 (20060101) AbstractA programmable logic array is disclosed employing arrays of electrically erasable and programmable cells. The device includes a dual purpose programming circuit which is employed to provide programming data to the AND array to program the AND array cells, and to provide OR array row selection data during OR array programming, thereby eliminating the need for a separate OR array row decoder. A method and apparatus is also disclosed for efficiently testing the AND array cells and input circuitry by bulk stripe programming the array cells.Other References
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