Grown side-wall silicided source/drain self-align CMOS fabrication process

Patent 4764481 Issued on August 16, 1988. Estimated Expiration Date:

August 24, 2007. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.

Abstract Claims Description Full Text

Patent References

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Patent #: 4364166
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Method for the manufacture of gate electrodes formed of double layers of metal silicides having a high melting point and doped polycrystalline silicon Patent #: 4640844
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Inventor: Neppl , et al.

Inventors

Assignee

Delco Electronics Corporation

Application

No. 07/088238 filed on 08/24/1987

US Classes:

438/227, Having well structure of opposite conductivity type257/750, Layered257/E21.151, Applied layer being silicon or silicide or SIPOS, e.g., polysilicon, porous silicon (EPO)257/E21.507, Formation of contacts to semiconductor by use of metal layers separated by insulating layers, e.g., self-aligned contacts to source/drain or emitter/base (EPO)257/E21.634, With particular manufacturing method of source or drain, e.g., specific S or D implants or silicided S or D structures or raised S or D structures (EPO)438/231, Plural doping steps438/232, Plural doping steps438/233And contact formation

Examiners

Primary: Hearn, Brian E.
Assistant: Quach, T. N.

Attorney, Agent or Firm

Wallace; Robert J.

International Classes

H01L 21/02 (20060101)
H01L 21/70 (20060101)
H01L 21/60 (20060101)
H01L 21/8238 (20060101)
H01L 21/225 (20060101)

Abstract

A process for forming CMOS devices uses outdiffusion of implanted ions in a patterned refractory silicidable layer to form the source/drain regions of the device. Moreover, the oxidation of the sidewalls of openings formed in the layer serves to isolate the layer from the polysilicon gate electrode which is later formed in the openings in this layer.

Other References

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S. Ogura, C. F. Codella, N. Rovedo, J. F. Shepard, and J. Riseman, "A Half Micron MOSFET Using Double Implanted LDD", IEDM Tech. Dig., pp. 718-721, 1982
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M-L Chen et al., "A High Performance Submicron CMOS Process with Self-aligned Chan-Stop and Punch-Through Implants (Twin-Tub V)," IEEE IEDM, pp. 256-259
K. Tsukamoto et al., "Self-Aligned Titanium Silicidation of Submicron MOS Devices by Rapid Lamp Annealing," IEEE IEDM 1984, pp. 130-133
K. Balasubramanyam et al., "Characterization of As-P Double Diffused Drain Structure," IEEE IEDM, 1984, pp. 782-785
D. L. Kwong and N. S. Alvi, "A Novel Silicided Shallow Junction Technology for CMOS VLSI," Published in: Material Issues in Silicon Integrated Circuit Processing, M. Wiltmer ed., Materials Research Society, 1986
D. L. Kwong, D. C. Meyers, and N. S. Alvi, "Simultaneous Formation of Silicide Ohmic Contacts and Shallow p³⁰ -n Junctions by Ion-Beam Mixing and Rapid Thermal Annealing," IEEE Electron Device Letters, vol. EDL-6, No. 5, pp. 244-246, May 1985