U.S. patents available from 1976 to present.
U.S. patent applications available from 2005 to present.

CMOS latch-up recovery circuit

Patent 4761702 Issued on August 2, 1988. Estimated Expiration Date: Icon_subject November 20, 2006. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.

Patent References

Protective circuit for a switching regulator
Patent #: 4210947
Issued on: 07/01/1980
Inventor: Koizumi

Line variable overcurrent protection for a voltage conversion circuit
Patent #: 4415960
Issued on: 11/15/1983
Inventor: Clark, Jr.

Intrinsically safe power supply with a current regulator Patent #: 4646219
Issued on: 02/24/1987
Inventor: Rohl

Inventor

Assignee

Application

No. 06/932405 filed on 11/20/1986

US Classes:

361/18, Voltage regulator protective circuits361/75, With time delay before reclosing361/86, Voltage361/89, With time delay protective means363/21.1, Utilizing pulse-width modulation363/56.1Having current protection

Examiners

Primary: Pellinen, A. D.
Assistant: DeBoer, Todd E.

Attorney, Agent or Firm

International Classes

H02M 3/335 (20060101)
H02H 7/12 (20060101)
H02M 3/24 (20060101)
H02M 1/00 (20060101)

Foreign Application Priority Data

1986-04-22 CA

Abstract

An overcurrent shut down circuit for use in a switching regulator power supply comprised of circuitry for detecting the average current of a pulse width modulated input signal, comparing the average current with a predetermined threshold level and reducing the duty cycle of the pulse width modulated signal to zero thereby shutting off the power supply, in the event the detected current exceeds the threshold level, indicating excess current being drawn from an output circuit of the supply. Time delay circuitry is provided for resetting the shut down circuit and restoring the regulator to normal operation after a predetermined amount of time as elapsed subsequent to the power supply being shut down. The overcurrent shut down circuit provides for recovery from CMOS latch-up and other excess current drawing fault conditions without requiring that the power supply be manually turned off. The circuit is of straightforward and inexpensive design and occupies very little circuit board area.

PatentsPlus Images
Enhanced PDF formats
loading...
PatentsPlus: add to cart
PatentsPlus: add to cartSearch-enhanced full patent PDF image
$9.95more info
PatentsPlus: add to cart
PatentsPlus: add to cartIntelligent turbocharged patent PDFs with marked up images
$18.95more info
 
Sign InRegister
Username  
Password   
forgot password?