Abstract

A local area network packet receiving system synchronizes the passage of packets through a receive buffer through a synchronizing circuit which supplies clock pulses to the receive buffer. The clock system utilizes a sensing circuit that senses the rate at which packets are being stored in the receive buffer. A master oscillator provides a reference signal and a rate control circuit coupled to the sensing circuit controls the rate at which the clock pulses are supplied to the receive buffer. A programmable timer supplies timing pulses out of the control of the rate control circuit. A phase-lock-loop having first and second comparison inputs is coupled to the programmable timer to receive the timing pulses on the first comparison input and to the master oscillator to receive a reference signal on the second comparsion input. A pulse circuit is coupled to the phase-lock-loop to supply clock pulses which are derived from the output of the phase-lock-loop, and which have a pulse repetition rate that matches the rate at which packets are being stored in the receive buffer.