Full adder circuit using differential transistor pairs
Patent 4740907 Issued on April 26, 1988. Estimated Expiration Date: 
April 26, 2005. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.
April 26, 2005. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.Patent References 3519810 3906211 3906212 3925651 Integrated digital multiplier circuit using current mode logic Dynamic CMOS logic circuits for implementing multiple AND-functions MOS full adder circuit Patent #: 4583192 InventorsApplicationNo. 06/716090 filed on 03/26/1985US Classes:708/701Bipolar junction transistor only or combined with Field-Effect TransistorExaminersPrimary: Harkcom, Gary V.Assistant: Shaw, Dale M. Attorney, Agent or FirmInternational ClassesG06F 7/48 (20060101)G06F 7/50 (20060101) Foreign Application Priority Data1984-03-29 JPAbstractA high-speed full adder circuit comprising a plurality of differential transistor pairs and operating at multiple logic levels. This full adder can be made up of basic logic circuits, each having differential transistor pairs, such as exclusive-OR circuits, AND circuits and OR circuits. To reduce the chip size of the full adder, while ensuring a high-speed operation, transistors which may be used in common are replaced by a smaller number of transistors, thereby reducing the number of required transistors. | |
