U.S. patents available from 1976 to present.
U.S. patent applications available from 2005 to present.

Triggered, programmable skew signal generator

Patent 4739277 Issued on April 19, 1988. Estimated Expiration Date: Icon_subject March 3, 2006. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.

Patent References

3602824

3746997

Phase tracking network
Patent #: 3971996
Issued on: 07/27/1976
Inventor: Motley ,   et al.

Broadband phase shifter
Patent #: 4379264
Issued on: 04/05/1983
Inventor: Lenhardt

Phase control device
Patent #: 4485479
Issued on: 11/27/1984
Inventor: Iino ,   et al.

Skew detector
Patent #: 4646297
Issued on: 02/24/1987
Inventor: Palmquist ,   et al.

Method for measuring skew or phase difference in electronic systems Patent #: 4703448
Issued on: 10/27/1987
Inventor: Muething, Jr.

Inventors

Assignee

Application

No. 06/835412 filed on 03/03/1986

US Classes:

327/234, Dependent on variable controlled phase shifts327/232, Dependent on frequency327/246, With differential amplifier327/250, With active time delay element327/287Differential amplifier

Examiners

Primary: Miller, Stanley D.
Assistant: Callahan, Timothy P.

Attorney, Agent or Firm

International Classes

G01R 13/32 (20060101)
G01R 13/22 (20060101)

Abstract

A signal generator for producing a triggered output signal of digitally controlled phase and frequency includes a skewing circuit for producing an output clock signal of the same period, T, as an input, triggered reference clock signal but which is phase skewed from the reference clock signal by a phase angle, P, of 0 to 360 degrees as determined by input digital data. The skewed clock signal is frequency divided by an integer factor N, and a timing circuit counts reference clock periods to initiate frequency division a programmable delay time (J×T seconds) following triggering of the reference clock signal, where J and N are integers also determined by input digital data. An AND gate qualifies the frequency divided skewed clock signal with the skewed clock signal itself to produce a periodic output signal of digitally controlled frequency N/T, the first pulse of which is delayed following triggering of the reference signal by a digitally controlled interval of (T×J)+(P×T/360) seconds.

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