VDS clamp for limiting impact ionization in high density CMOS devices
November 14, 2006. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.Patent ReferencesMIS switching circuit capable of enduring high voltage High-voltage circuit for insulated gate field-effect transistor Switched-capacitor conductance-control of variable transconductance elements High voltage circuits in low voltage CMOS process Reduction of gate oxide breakdown for booted nodes in MOS integrated circuits Floating node stabilizing circuit for a switched-capacitor circuit and filter Switched capacitor filter utilizing a differential input and output circuit Patent #: 4633425 InventorApplicationNo. 06/930869 filed on 11/14/1986US Classes:327/546, With field-effect transistor327/541, With field-effect transistor327/560, Nonlinear amplifying circuit327/576, Complementary transistors330/253Having field effect transistorExaminersPrimary: Miller, Stanley D.Assistant: Hudspeth, D. R. Attorney, Agent or FirmInternational ClassesH03K 17/081 (20060101)H03K 17/08 (20060101) H03K 17/10 (20060101) H03F 1/52 (20060101) AbstractA circuit for controlling drain-to-source voltage in an MOS transistor. A second MOS transistor is located in series with the first transistor. The gate voltage of the second transistor is such that the drain-to-source voltages of both transistors are substantially equal. | |
