Patent ReferencesSemiconductor device Method of making electrode wiring regions and impurity doped regions self-aligned therefrom Method of manufacturing a metal-insulator-semiconductor device utilizing a graded deposition of polycrystalline silicon Polysilicon-base self-aligned bipolar transistor process Process for manufacturing integrated bi-polar transistors of very small dimensions Double self-aligned fabrication process for making a bipolar transistor structure having a small polysilicon-to-extrinsic base contact area Forming chan-stops by selectively implanting impurity ions through field-oxide layer during later stage of MOS-device fabrication Bipolar transistors having vertically arrayed collector-base-emitter with novel polycrystalline base electrode surrounding island emitter and method of making same Method for the manufacture of bipolar transistor structures with self-adjusting emitter and base regions for extreme high frequency circuits Method of fabricating an insulated gate type field-effect transistor Patent #: 4616401 InventorsAssigneeApplicationNo. 07/013252 filed on 02/10/1987US Classes:438/234, Including bipolar transistor (i.e., BiMOS)257/370, Combined with bipolar transistor257/374, Dielectric isolation means (e.g., dielectric layer in vertical grooves)257/E21.038, Characterized by process involved to create mask, e.g., lift-off mask, sidewalls, or to modify mask, such as pre-treatment, post-treatment (EPO)257/E21.312, Of silicon-containing layer (EPO)257/E21.375, Silicon vertical transistor (EPO)257/E21.444, Using dummy gate wherein at least part of final gate is self-aligned to dummy gate (EPO)257/E21.696, Bipolar and MOS technologies (EPO)257/E29.255, With field effect produced by insulated gate (EPO)438/303, Utilizing gate sidewall structure438/305, Plural doping steps438/366, Having sidewall438/372Plural doping stepsExaminersPrimary: Ozaki, George T.Attorney, Agent or FirmInternational ClassesH01L 21/70 (20060101)H01L 21/033 (20060101) H01L 21/336 (20060101) H01L 21/02 (20060101) H01L 21/3213 (20060101) H01L 29/66 (20060101) H01L 29/78 (20060101) H01L 21/331 (20060101) H01L 21/8249 (20060101) Foreign Application Priority Data1986-07-09 JPAbstractA method of fabricating a semiconductor device includes the steps of: forming at least one first semiconductor region of a first conductivity type and at least one second semiconductor region of a second conductivity type in a main surface of a semiconductor layer of the first conductivity type; forming a three-layer film having a desired shape on each of the first and second semiconductor regions, the three-layer film being made up of a bottom layer which is a conductive film, an intermediate layer which is a silicon nitride film, and a top layer which is a polycrystalline silicon film doped with one of arsenic and phosphorus; forming a first insulating layer on the side wall of the three-layer film; forming a second polycrystalline silicon film on the whole surface, and diffusing one of arsenic and phosphorus from the first polycrystalline silicon film into the second polycrystalline silicon film; selectively etching off the first polycrystalline silicon film and that portion of the second polycrystalline silicon film, in which one of arsenic and phosphorus has been diffused; forming a second insulating layer at least on the surface of the portion of the second polycrystalline silicon film which exists on the second semiconductor region; removing the silicon nitride film and the conductive film which exist on the second semiconductor region, while using the second insulating layer as a mask, to form an aperture; and forming a third polycrystalline silicone film so that the aperture is covered by the third polycrystalline silicon film. | |