U.S. patents available from 1976 to present.
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Method of fabricating bipolar transistors and insulated gate field effect transistors having doped polycrystalline silicon conductors

Patent 4735916 Issued on April 5, 1988. Estimated Expiration Date: Icon_subject February 10, 2007. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.

Patent References

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Patent #: 4127931
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Inventor: Shiba

Method of making electrode wiring regions and impurity doped regions self-aligned therefrom
Patent #: 4306915
Issued on: 12/22/1981
Inventor: Shiba

Method of manufacturing a metal-insulator-semiconductor device utilizing a graded deposition of polycrystalline silicon
Patent #: 4354309
Issued on: 10/19/1982
Inventor: Gardiner ,   et al.

Polysilicon-base self-aligned bipolar transistor process
Patent #: 4381953
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Process for manufacturing integrated bi-polar transistors of very small dimensions
Patent #: 4481706
Issued on: 11/13/1984
Inventor: Roche

Double self-aligned fabrication process for making a bipolar transistor structure having a small polysilicon-to-extrinsic base contact area
Patent #: 4483726
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Forming chan-stops by selectively implanting impurity ions through field-oxide layer during later stage of MOS-device fabrication
Patent #: 4494304
Issued on: 01/22/1985
Inventor: Yoshioka

Bipolar transistors having vertically arrayed collector-base-emitter with novel polycrystalline base electrode surrounding island emitter and method of making same
Patent #: 4531282
Issued on: 07/30/1985
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Method for the manufacture of bipolar transistor structures with self-adjusting emitter and base regions for extreme high frequency circuits
Patent #: 4581319
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Method of fabricating an insulated gate type field-effect transistor Patent #: 4616401
Issued on: 10/14/1986
Inventor: Takeuchi

Inventors

Assignee

Application

No. 07/013252 filed on 02/10/1987

US Classes:

438/234, Including bipolar transistor (i.e., BiMOS)257/370, Combined with bipolar transistor257/374, Dielectric isolation means (e.g., dielectric layer in vertical grooves)257/E21.038, Characterized by process involved to create mask, e.g., lift-off mask, sidewalls, or to modify mask, such as pre-treatment, post-treatment (EPO)257/E21.312, Of silicon-containing layer (EPO)257/E21.375, Silicon vertical transistor (EPO)257/E21.444, Using dummy gate wherein at least part of final gate is self-aligned to dummy gate (EPO)257/E21.696, Bipolar and MOS technologies (EPO)257/E29.255, With field effect produced by insulated gate (EPO)438/303, Utilizing gate sidewall structure438/305, Plural doping steps438/366, Having sidewall438/372Plural doping steps

Examiners

Primary: Ozaki, George T.

Attorney, Agent or Firm

International Classes

H01L 21/70 (20060101)
H01L 21/033 (20060101)
H01L 21/336 (20060101)
H01L 21/02 (20060101)
H01L 21/3213 (20060101)
H01L 29/66 (20060101)
H01L 29/78 (20060101)
H01L 21/331 (20060101)
H01L 21/8249 (20060101)

Foreign Application Priority Data

1986-07-09 JP

Abstract

A method of fabricating a semiconductor device includes the steps of: forming at least one first semiconductor region of a first conductivity type and at least one second semiconductor region of a second conductivity type in a main surface of a semiconductor layer of the first conductivity type; forming a three-layer film having a desired shape on each of the first and second semiconductor regions, the three-layer film being made up of a bottom layer which is a conductive film, an intermediate layer which is a silicon nitride film, and a top layer which is a polycrystalline silicon film doped with one of arsenic and phosphorus; forming a first insulating layer on the side wall of the three-layer film; forming a second polycrystalline silicon film on the whole surface, and diffusing one of arsenic and phosphorus from the first polycrystalline silicon film into the second polycrystalline silicon film; selectively etching off the first polycrystalline silicon film and that portion of the second polycrystalline silicon film, in which one of arsenic and phosphorus has been diffused; forming a second insulating layer at least on the surface of the portion of the second polycrystalline silicon film which exists on the second semiconductor region; removing the silicon nitride film and the conductive film which exist on the second semiconductor region, while using the second insulating layer as a mask, to form an aperture; and forming a third polycrystalline silicone film so that the aperture is covered by the third polycrystalline silicon film.

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