Abstract

A semiconductor device which is provided with a surface channel type or bulk channel type MIS FET. The MIS FET comprises at least a semiconductor substrate of a first conductivity type, a layer member formed in a predetermined pattern on the major surface of the substrate and having an insulating side surface; an insulating layer formed on the major surface of the substrate to extend from the insulating side surface in a direction opposite from the layer member; a conductive layer formed on the major surface of the insulating layer in contact with the insulating side surface of the layer member; and a first semiconductor region of a second conductivity type formed in the semiconductor substrate having a marginal edge corresponding to that of the conductive layer. The first semiconductor region serves as either one of source and drain regions; that region of the semiconductor substrate underlying the conductive layer serves as a channel forming region; that region of the conductive layer facing the channel forming region serves as a gate electrode; and that region of the insulating layer underlying the gate electrode serves as a gate insulating layer. The MIS FET can easily be combined with another MIS FET, a resistance element or capacitance element which is formed through utilization of the layer member of the former.