ApplicationNo. 06/643260 filed on 08/22/1984
US Classes:326/42, Bipolar transistor257/E27.102, Read-only memory, ROM, structure (EPO)326/100, INTEGRATED INJECTION LOGIC326/44Field effect transistor
ExaminersPrimary: Heyman, John S.
Assistant: Wambach, M. R.
Attorney, Agent or Firm
International ClassesH03K 19/0944 (20060101)
H03K 19/177 (20060101)
H01L 27/112 (20060101)
Foreign Application Priority Data1983-08-22 JP
AbstractAn integrated programmable logic array formed within a single silicon chip comprises a combination of a logical product gate array and a logical summation gate array. The logical product gate array is equipped with a plurality of MIS field-effect transistors whose gates are selectively driven by a plurality of input signals. Source-drain paths of these transistors are connected in series. The logical summation gate array is equipped with a plurality of inverted bipolar transistors having collector-emitter paths which are connected in parallel.