MOS logic circuit
High-speed, low consumption integrated logic circuit
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A field effect transistor logic gate having depletion mode and enhancement mode transistors
Logic circuit including at least one resistor or one transistor having a saturable resistor field effect transistor structure
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ApplicationNo. 06/856630 filed on 04/25/1986
US Classes:326/117, Depletion or enhancement326/83Field-effect transistor
ExaminersPrimary: Miller, Stanley D.
Assistant: Hudspeth, D. R.
Attorney, Agent or Firm
International ClassesH03K 19/0944 (20060101)
H03K 19/01 (20060101)
H03K 19/017 (20060101)
AbstractDigital logic driving stage circuitry is provided connected between ground and a single voltage with an enhancement mode type field effect transistor and a depletion mode type field effect transistor connected source to drain in series between the single voltage and ground. The gate of the enhancement mode type field effect transistor is the input of the logic signal and the gate of the depletion mode type field effect transistor is connected to ground, with the output at the connection between the transistors. A family of digital logic circuits is provided with circuit units made up of an enhancement mode logic input, depletion mode load circuitry stage and an enhancement mode input grounded source follower load driving stage.