Two-stage digital logic circuits including an input switching stage and an output driving stage incorporating gallium arsenide FET devices
Patent 4725743 Issued on February 16, 1988. Estimated Expiration Date: April 25, 2006. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.
Digital logic driving stage circuitry is provided connected between ground and a single voltage with an enhancement mode type field effect transistor and a depletion mode type field effect transistor connected source to drain in series between the single voltage and ground. The gate of the enhancement mode type field effect transistor is the input of the logic signal and the gate of the depletion mode type field effect transistor is connected to ground, with the output at the connection between the transistors. A family of digital logic circuits is provided with circuit units made up of an enhancement mode logic input, depletion mode load circuitry stage and an enhancement mode input grounded source follower load driving stage.
Other References
Yokoyama et al., "GaAs MOSFET High-Speed Logic"; Third (3rd) Int'l. Conf. on Solid-State Devices, Tokyo, JP., 1979, 17 pages
Schuermeyer, "GaAs IGFET Digital Integrated Circuits", IEEE Trans. on Electron Devices, vol. ED-28, No. 5, pp. 541-545; 5/1981
Schuermeyer et al., "GaAs IGFET: A New Device for High Speed Digital IC's"; Int'l. Electron Devices Meeting, 12/1980
Schuermeyer et al., "Trap Studies on GaAs-Si3 N4 Interfaces"; J. Vac. Sci. Technol., 19(3), Sep./Oct. 1981; pp. 421-426
IEEE Int'l. Conf. Solid-State Circuits 2/15/78, "Low Power GaAs Digital ICs Using Schottky Diode-FET Logic", by R. C. Eden et al., pp. 68-69
IEEE Journal of Solid-State Circuits, vol. SC-9, No. 5, Oct. 1974, pp. 269-276, "High-Speed Integrated Logic with GaAs MESFET's", by Van Tuyl et al
IEEE Journal of Solid-State Circuits, vol. SC-11, No. 3, Jun. 1976, pp. 385-394, "A Subnanosecond Integrated Switching Circuit with MESFET's for LSI"--Nuzillat et al
IEEE Electron Device Letters, vol. EDL-3, No. 8, Aug. 1982, pp. 197-199, "A GaAs Monolithic Frequency Divider Using Source Coupled FET Logic", by S. Katsu et al
IEE Proc., vol. 127, Pt. 1, No. 5, (Oct. 1980), pp. 287-296, "Low Pinch-off voltage f.e.t. logic (l.p.f.l.): l.s.i. oriented logic approach using quasinonmally off GaAs m.e.s.f.e.t.s.", by Nuzillat et al
IEEE Transactions on Electron Devices, vol. ED-26, No. 4, Apr. 1979, pp. 299-317, "The Prospects for Ultrahigh-Speed VLSI GaAs Digital Logic", by Eden et al
IEEE Transactions on Electron Devices, vol. ED-29, No. 3, Mar. 1982, pp. 402-410, "The Effect of Logic Cell Configuration, Gatelength, and Fan-Out on the Propagation Delays of GaAs MESFET Logic Gates", by Namordi et al
Electronics, (Oct. 9, 1980), pp. 76 & 78, "Gallium Arsenide to yield 5-GHz Divider", by K. Dreyfack
IEEE Journal of Solid-State Circuits, vol. SC-12, No. 5, (Oct. 1977), "GaAs MESFET Logic with 4-GHz Clock Rate", by Van Tuyl et al
Electronics, (Jun. 14, 1963), pp. 43-45, "Put More Snap in Logic Circuits With Field-Effect Transistors", by Csanky et al
Electronics Letters, (4th Feb. 1982), vol. 18, No. 3, pp. 109-110, "High-Speed Two-Dimensional Electron-Gas FET Logic", by Tung et al
April 25, 2006. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.
