U.S. patents available from 1976 to present.
U.S. patent applications available from 2005 to present.

Semiconductor integrated circuit device

Patent 4717684 Issued on January 5, 1988. Estimated Expiration Date: Icon_subject February 3, 2006. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.

Patent References

3731161

Insulated gate field effect transistor with source field shield extending over multiple region channel
Patent #: 4172260
Issued on: 10/23/1979
Inventor: Okabe ,   et al.

Breakdown voltage resistor obtained through a double ion-implantation into a semiconductor substrate, and manufacturing process of the same
Patent #: 4298401
Issued on: 11/03/1981
Inventor: Nuez ,   et al.

Process for monolithic integration of logic, control, and high voltage interface circuitry
Patent #: 4325180
Issued on: 04/20/1982
Inventor: Curran

Fabrication of submicron semiconductor devices
Patent #: 4356623
Issued on: 11/02/1982
Inventor: Hunter

Semiconductor device and method for production thereof
Patent #: 4399451
Issued on: 08/16/1983
Inventor: Shirai

Storage capacitor optimization for one device FET dynamic RAM cell
Patent #: 4466177
Issued on: 08/21/1984
Inventor: Chao

Method of making an integrated circuit incorporating low voltage and high voltage semiconductor devices
Patent #: 4475280
Issued on: 10/09/1984
Inventor: Ragonese ,   et al.

Method of manufacturing an MIS type semiconductor device
Patent #: 4502205
Issued on: 03/05/1985
Inventor: Yahano

Method of manufacturing an insulated-gate field-effect transistor
Patent #: 4575920
Issued on: 03/18/1986
Inventor: Tsunashima

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Inventors

Assignee

Application

No. 06/825587 filed on 02/03/1986

US Classes:

438/200, And additional electrical device257/336, With lightly doped portion of drain region adjacent channel (e.g., LDD structure)257/E21.64, With particular manufacturing method of gate sidewall spacers, e.g., double spacers, particular spacer material or shape (EPO)257/E21.654, Characterized by type of transistor; manufacturing of transistor (EPO)257/E27.064, Combination of complementary transistors having a different structure, e.g. stacked CMOS, high-voltage and low-voltage CMOS (EPO)257/E29.255, With field effect produced by insulated gate (EPO)438/238, Including passive device (e.g., resistor, capacitor, etc.)438/275, Making plural insulated gate field effect transistors of differing electrical characteristics438/305Plural doping steps

Examiners

Primary: Hearn, Brian E.
Assistant: Thomas, Tom

Attorney, Agent or Firm

International Classes

H01L 21/70 (20060101)
H01L 29/66 (20060101)
H01L 29/78 (20060101)
H01L 21/8238 (20060101)
H01L 27/02 (20060101)
H01L 27/092 (20060101)
H01L 27/085 (20060101)
H01L 21/8242 (20060101)

Foreign Application Priority Data

1985-02-01 JP

Abstract

A semiconductor integrated circuit device wherein the source and drain regions of a MOSFET in an internal circuit have lightly doped drain (LDD) structures in order to suppress the appearance of hot carriers, and the source and drain regions of a MOSFET in an input/output circuit have structures doped with phosphorus at a high impurity concentration, in order to enhance an electrostatic breakdown voltage.

Other References

  • Ralhmam, "An Optimized 0.5 Micron LDD Transistor", IEDM, 1983, pp. 237-239
  • Oguna, "Design and Characteristics of the Lightly Doped Drain-Source (LDD) Insulated Gate Field-Effect Transistor" IEEE Trans. on Electron Devices, ED 27, Aug. 80, pp. 1359-1367
  • Tsang, "Fabrication of High Performance LDDFETS with Oxide Sidewall-Spacer Technology," IEEE Journal of Solid State Circuits, vol. SC-17, No. 2, Apr. 82, pp. 220-226
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