Patent References 3731161 Insulated gate field effect transistor with source field shield extending over multiple region channel Breakdown voltage resistor obtained through a double ion-implantation into a semiconductor substrate, and manufacturing process of the same Process for monolithic integration of logic, control, and high voltage interface circuitry Fabrication of submicron semiconductor devices Semiconductor device and method for production thereof Storage capacitor optimization for one device FET dynamic RAM cell Method of making an integrated circuit incorporating low voltage and high voltage semiconductor devices Method of manufacturing an MIS type semiconductor device Method of manufacturing an insulated-gate field-effect transistor InventorsAssigneeApplicationNo. 06/825587 filed on 02/03/1986US Classes:438/200, And additional electrical device257/336, With lightly doped portion of drain region adjacent channel (e.g., LDD structure)257/E21.64, With particular manufacturing method of gate sidewall spacers, e.g., double spacers, particular spacer material or shape (EPO)257/E21.654, Characterized by type of transistor; manufacturing of transistor (EPO)257/E27.064, Combination of complementary transistors having a different structure, e.g. stacked CMOS, high-voltage and low-voltage CMOS (EPO)257/E29.255, With field effect produced by insulated gate (EPO)438/238, Including passive device (e.g., resistor, capacitor, etc.)438/275, Making plural insulated gate field effect transistors of differing electrical characteristics438/305Plural doping stepsExaminersPrimary: Hearn, Brian E.Assistant: Thomas, Tom Attorney, Agent or FirmInternational ClassesH01L 21/70 (20060101)H01L 29/66 (20060101) H01L 29/78 (20060101) H01L 21/8238 (20060101) H01L 27/02 (20060101) H01L 27/092 (20060101) H01L 27/085 (20060101) H01L 21/8242 (20060101) Foreign Application Priority Data1985-02-01 JPAbstractA semiconductor integrated circuit device wherein the source and drain regions of a MOSFET in an internal circuit have lightly doped drain (LDD) structures in order to suppress the appearance of hot carriers, and the source and drain regions of a MOSFET in an input/output circuit have structures doped with phosphorus at a high impurity concentration, in order to enhance an electrostatic breakdown voltage.Other References
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