Method of making a heterojunction bipolar transistor with SIPOS
Patent 4717681 Issued on January 5, 1988. Estimated Expiration Date: 
May 19, 2006. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.
May 19, 2006. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.Patent References 3394289 3488235 3878552 3913124 Method of making a bipolar transistor Complementary semiconductor device Method of fabricating self-aligned bipolar transistor process and device utilizing etching and self-aligned masking Molecular beam converters for vacuum coating systems Method of producing an IIL semiconductor device utilizing self-aligned thickened oxide patterns Microwave transistor InventorAssigneeApplicationNo. 06/864671 filed on 05/19/1986US Classes:438/314, And additional electrical device257/197, Bipolar transistor257/760, Separating insulating layer is laminate or composite of plural insulating materials (e.g., silicon oxide on silicon nitride, silicon oxynitride)257/914, POLYSILICON CONTAINING OXYGEN, NITROGEN, OR CARBON (E.G., SIPOS)257/E21.121, Substrate is crystalline insulating material, e.g., sapphire (EPO)257/E21.13, The substrate is crystalline conducting material, e.g., metallic silicide (EPO)257/E21.223, Anisotropic liquid etching (EPO)257/E21.251, By chemical means (EPO)257/E21.259, Organic layers, e.g., photoresist (EPO)257/E21.266, Inorganic layer (EPO)257/E21.309, By liquid etching only (EPO)257/E21.371, Heterojunction transistor (EPO)257/E21.614, Three-dimensional integrated circuits stacked in different levels (EPO)257/E27.026, Integrated circuit having a three-dimensional layout (EPO)438/311, On insulating substrate or layer (i.e., SOI type)438/341, Using epitaxial lateral overgrowth438/481, Utilizing epitaxial lateral overgrowth438/958PASSIVATION LAYERExaminersPrimary: Hearn, Brian E.Assistant: Bunch, William Attorney, Agent or FirmInternational ClassesH01L 21/306 (20060101)H01L 21/02 (20060101) H01L 21/70 (20060101) H01L 21/00 (20060101) H01L 21/20 (20060101) H01L 21/3213 (20060101) H01L 21/311 (20060101) H01L 21/312 (20060101) H01L 21/822 (20060101) H01L 21/331 (20060101) H01L 21/314 (20060101) H01L 27/06 (20060101) AbstractA wafer process flow encompasses an arbitray repeated layered structure of heteroepitaxial layers of silicon based films with process control throughout the strata of chemical potential and recombination velocity, suitable for both high performance MOS and bipolar transistors with three dimensional transistor capability. A non-compensated doping technique preserves crystalline periodicity, as does the component delineation by means of anisotropic etching. The wafer is hermetic by means of the semi-insulation films polyimide, and the elimination of phosphorous doped silicon dioxide. A metallurgy system enables a high level integration.Other References
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