U.S. patents available from 1976 to present.
U.S. patent applications available from 2005 to present.

Display refresh memory apparatus utilizing one half frame updating

Patent 4716460 Issued on December 29, 1987. Estimated Expiration Date: Icon_subject October 8, 2006. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.

Patent References

Video processing system
Patent #: 4148070
Issued on: 04/03/1979
Inventor: Taylor

Video overlay system having interactive color addressing
Patent #: 4484187
Issued on: 11/20/1984
Inventor: Brown ,   et al.

Horizontal and vertical image inversion circuit for a video display
Patent #: 4570158
Issued on: 02/11/1986
Inventor: Bleich ,   et al.

Progressive scan television receiver with adaptive memory addressing
Patent #: 4573080
Issued on: 02/25/1986
Inventor: Maze

Field number conversion circuit
Patent #: 4587557
Issued on: 05/06/1986
Inventor: Doornhein ,   et al.

Arrangement for processing data in digital fluorographic systems
Patent #: 4590518
Issued on: 05/20/1986
Inventor: Fenster ,   et al.

Raster display generator for hybrid display system
Patent #: 4631532
Issued on: 12/23/1986
Inventor: Grothe

Scanning conversion method and scan converter unit employing the conversion method Patent #: 4658293
Issued on: 04/14/1987
Inventor: Arai ,   et al.

Inventors

Assignee

Application

No. 06/916580 filed on 10/08/1986

US Classes:

348/458, Changing number of lines for standard conversion345/539, Double buffered348/705Switching

Examiners

Primary: Britton, Howard W.

Attorney, Agent or Firm

International Classes

G09G 5/36 (20060101)
G09G 5/39 (20060101)

Abstract

Refresh memory apparatus for use in a CRT raster display system utilizes half field storage memories for ping ponging between updating and readout. In one TV mode of operation the even and odd raster lines are stored in the respective memories and in another TV mode the top and bottom halves of the frame are stored therein. The most significant bit and least significant bit of the vertical address signals are multiplexed to control the ping pong reading and writing of the memories and are multiplexed with the remainder of the address signal to provide the read and write addresses for the memories. The multiplexers are controlled in accordance with the TV mode in which the system is operating.

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