Multiprocessor computing system featuring shared global control

Patent 4713834 Issued on December 15, 1987. Estimated Expiration Date:

June 20, 2006. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.

Abstract Claims Description Full Text

Patent References

3710324

System and method for accessing memory connected to different bus and requesting subsystem
Patent #: 4205373
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Common front-end control for a peripheral controller connected to a computer Patent #: 4322792
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Inventor: Baun

Inventors

Application

No. 06/876407 filed on 06/20/1986

US Classes:

379/28, Of data transmission instrument379/269Distributed control

Examiners

Primary: Shaw, Gareth D.
Assistant: Mills, John G.

Attorney, Agent or Firm

Volejnicek; David

International Class

G06F 12/06 (20060101)

Abstract

A multiprocessor system comprises a plurality of stations interconnected by a system communication bus and cooperating in the performance of system tasks. Each station includes a plurality of addressable elements interconnected by a station communication bus. All stations are mapped into a common address space, with the elements of each station mapped onto like relative addresses in two subspaces of the address space: a subspace which is shared in common by all stations, and a subspace dedicated to the station whose addresses are the common subspace addresses in combination with a station-identifying address portion. The stations are symmetrical: like elements in all of the stations are mapped onto like relative addresses in their associated subspaces. Addressing within the system is self-referential: a station accesses one of its addressable elements by placing its common subspace address on the station communication bus. Each station's station bus is selectively interfaced to the system bus, and a station accesses an addressable element of another station by placing its dedicated subspace address on the station bus, interfacing its station bus with the system bus, and causing the other station to interface its station bus with the system bus. A station accesses an element of another station passively, without utilizing the intelligence, if any, of the other station to make the access.

Other References

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