Manufacturing MOS semiconductor device with planarized conductive layer

Patent 4713356 Issued on December 15, 1987. Estimated Expiration Date:

February 27, 2006. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.

Abstract Claims Description Full Text

Patent References

Method for forming ultra fine deep dielectric isolation
Patent #: 4274909
Issued on: 06/23/1981
Inventor: Venkataraman , et al.

Method for producing integrated MOS field effect transistors with an additional track level of metal silicides
Patent #: 4462149
Issued on: 07/31/1984
Inventor: Schwabe

Method of forming self-aligned contact openings
Patent #: 4512073
Issued on: 04/23/1985
Inventor: Hsu

Method of fabricating an insulated gate type field-effect transistor Patent #: 4616401
Issued on: 10/14/1986
Inventor: Takeuchi

Inventor

Hiruta, Yoichi

Application

No. 06/833594 filed on 02/27/1986

US Classes:

438/297, Recessed oxide formed by localized oxidation (i.e., LOCOS)257/752, Planarized to top of insulating layer257/E21.168, Conductive layer comprising transition metal, e.g., Ti, W, Mo (EPO)257/E21.433, Where the source and drain or source and drain extensions are self-aligned to sides of gate (EPO)257/E21.59, Local interconnects; local pads (EPO)438/301, Source or drain doping438/586Combined with formation of ohmic contact to semiconductor region

Examiners

Primary: Chaudhuri, Olik

Attorney, Agent or Firm

Finnegan, Henderson, Farabow, Garrett & Dunner

International Classes

H01L 21/02 (20060101)
H01L 21/70 (20060101)
H01L 21/336 (20060101)
H01L 21/285 (20060101)
H01L 21/768 (20060101)

Foreign Application Priority Data

1985-02-28 JP

Abstract

A method of manufacturing a semiconductor device wherein the proportion of the area occupied by the source and drain regions can be reduced. In this method, the side walls of a gate electrode are first selectively deposited with an insulating film, then conductive material layers are selectively formed on the source and drain regions, partially extending to side portions of an element isolation regions, and, after forming an insulating protective film over the entire surface of the resultant structure, contact holes are formed to reach the conductive material layers for forming source and drain wiring layers.

Other References

Gargini et al., "WOS: Low-Resistance Self-Aligned Source, Drain and Gate Transistors", Technical Digest of IEDM, pp. 54-57, (1981)
Moriya et al., "Encroachment-Free Tungsten CVD Process for Self-Aligned Source-Drain-Gate Mettalization", Digest of Technical Papers of Symposium on VLSI Technology, No. 83, (1983)