Method of making a planar structure containing MOS and bipolar transistors

Patent 4707456 Issued on November 17, 1987. Estimated Expiration Date:

September 18, 2005. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.

Abstract Claims Description Full Text

Patent References

Method of forming polycrystalline silicon lines and vias on a silicon substrate
Patent #: 4319954
Issued on: 03/16/1982
Inventor: White , et al.

Method of making contact electrodes to silicon gate, and source and drain regions, of a semiconductor device
Patent #: 4343082
Issued on: 08/10/1982
Inventor: Lepselter , et al.

Method of manufacturing a semiconductor integrated circuit BI-MOS device
Patent #: 4445268
Issued on: 05/01/1984
Inventor: Hirao

Method of fabricating n-type silicon regions and associated contacts Patent #: 4542580
Issued on: 09/24/1985
Inventor: Delivorias

Inventors

Assignee

Advanced Micro Devices, Inc.

Application

No. 06/777153 filed on 09/18/1985

US Classes:

438/207, Including isolation structure257/378, Combined with bipolar transistor257/518, With polycrystalline connecting region (e.g., polysilicon base contact)257/E21.552, Using local oxidation of silicon, e.g., LOCOS, SWAMI, SILO (EPO)257/E21.572, Polycrystalline semiconductor regions (EPO)257/E21.696, Bipolar and MOS technologies (EPO)257/E27.015, In combination with bipolar transistor (EPO)438/234, Including bipolar transistor (i.e., BiMOS)438/426, Recessed oxide laterally extending from groove438/442With epitaxial semiconductor layer formation

Examiners

Primary: Hearn, Brian E.
Assistant: Bunch, William

Attorney, Agent or Firm

International Classes

H01L 21/70 (20060101)
H01L 21/762 (20060101)
H01L 21/763 (20060101)
H01L 21/8249 (20060101)
H01L 27/06 (20060101)

Abstract

A highly planarized integrated circuit structure having at least one bipolar device and at least one MOS device is described as well as a method of making the structure. The structure comprises a substrate having a field oxide grown thereon with portions defined therein respectively for formation of a collector region and a base/emitter region for a bipolar device and a source/gate/drain region for an MOS device. All of the contacts of the devices are formed using polysilicon which fills the defined portions in the field oxide resulting in the highly planarized structure.