Output control circuit to prevent output of initial spike noise
Patent 4698529 Issued on October 6, 1987. Estimated Expiration Date: 
May 20, 2005. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.
May 20, 2005. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.Patent References 3774053 Electronic circuit using field effect transistor with compensation means Circuit for setting an initial state after connection of a power supply Dynamic logic gate Output circuit Patent #: 4345172 InventorAssigneeApplicationNo. 06/736029 filed on 05/20/1985US Classes:327/310, Transient or signal noise reduction327/313, Using 3 or more terminal type nonlinear devices only327/328, Field-effect type device327/392Delay controlled switch (e.g., fixed, single time of delay control, etc.)ExaminersPrimary: Miller, Stanley D.Assistant: Callahan, Timothy P. Attorney, Agent or FirmInternational ClassH03K 17/22 (20060101)Foreign Application Priority Data1984-05-30 JPAbstractInitial spike noise which occurs, when an IC is switched on, is suppressed by an output control circuit provided between the output terminal of an inner logic circuit and an output circuit of the IC. The output control circuit clamps the input terminal of the output control circuit until the supply voltage builds up to a steady state. The output control circuit comprises two stages each connected between the supply voltage and ground. The first stage has a series connection of a first FET and first resistor, the second stage has a series connection of a second FET, third FET and second resistor. The first FET is controlled by a reset signal and turns off the second FET until the reset signal is released. The second FET turns off the third FET which transmits the output signal of the inner circuit to the output circuit of the IC. When the reset signal is released, the third FET and hence the output circuit begins operation.Other References
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