Word processor apparatus having means for recording a tab function as a signal indicative of the number of spaces tabbed
Data processing apparatus for highly parallel execution of data structure operations
Reduction processor for executing programs stored as treelike graphs employing variable-free applicative language codes
Concurrent network of reduction processors for executing programs stored as treelike graphs employing variable-free applicative language codes
Programmable controller with intelligent positioning I/O modules Patent #: 4510565
ApplicationNo. 06/632564 filed on 07/19/1984
US Classes:707/206, Garbage collection711/173Memory partitioning
ExaminersPrimary: Eng, David Y.
Attorney, Agent or Firm
International ClassG06F 12/02 (20060101)
AbstractA method and apparatus for managing a block oriented memory of the type in which each memory block has an associated reference count representing the number of pointers to it from other memory blocks and itself. Efficient and cost-effective implementation of reference counting alleviates the need for frequent garbage collection, which is an expensive operation. The apparatus includes a hash table into which the virtual addresses of blocks of memory which equal zero are maintained. When the reference count of a block increases from zero, its virtual address is removed from the table. When the reference count of a block decreases to zero, its virtual address is inserted into the table. When the table is full, a reconciliation operation is performed to identify those addresses which are contained in a set of binding registers associated with the CPU, and any address not contained in the binding registers are evacuated into a garbage buffer for subsequent garbage collection operations. The apparatus can be implemented by a cache augmented by the hash table, providing a back-up store for the cache.