Computer vector register processing
High speed buffer memory system with word prefetch
Cache control for concurrent access
Multi-configurable cache store system
Relating to cached multiprocessor system with pipeline timing
Memory management unit for developing multiple physical addresses in parallel for use in a cache memory
Data processing machine with improved cache memory management
Dual port cache with interleaved read accesses during alternate half-cycles and simultaneous writing
FIFO buffer to cache memory
Split-cycle cache system with SCU controlled cache clearing during cache store access period
ApplicationNo. 06/655473 filed on 09/27/1984
US Classes:711/140, Cache pipelining711/130Shared cache
ExaminersPrimary: Williams, Archie E. Jr.
Assistant: Anderson, Lawrence E.
Attorney, Agent or Firm
International ClassG06F 12/08 (20060101)
AbstractA cache memory unit is constructed to have a two-stage pipeline shareable by a plurality of sources which include two independently operated central processing units (CPUs). Apparatus included within the cache memory unit operates to allocate alternate time slots to the two CPUs which offset their operations by a pipeline stage. This permits one pipeline stage of the cache memory unit to perform a directory search for one CPU while the other pipeline stage performs a data buffer read for the other CPU. Each CPU is programmed to use less than all of the time slots allocated to it. Thus, the processing units operate conflict-free while pipeline stages are freed up for processing requests from other sources, such as replacement data from main memory or cache updates.