Pattern delineation of vertical load resistor
Patent 4690728 Issued on September 1, 1987. Estimated Expiration Date: 
October 23, 2006. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.
October 23, 2006. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.Patent References 3900944 Semiconductor integrated circuit with implanted resistor element in polycrystalline silicon layer Method of restoring semiconductor device performance Method of plasma etching of films containing chromium Patent #: 4445966 InventorsApplicationNo. 06/922289 filed on 10/23/1986US Classes:438/384, Deposited thin film resistor204/192.32, Sputter etching216/16, Forming or treating resistive material257/537, Using specific resistive material257/E21.004, Of resistor (EPO)257/E21.251, By chemical means (EPO)257/E21.252, By dry-etching (EPO)257/E27.101, Load element being a resistor (EPO)29/610.1, Resistor making29/620, Coating resistive material on a base338/308, Resistance element coated on base427/103, Applying superposed diverse coatings or coating a coated base438/653, At least one layer forms a diffusion barrier438/704Having liquid and vapor etching stepsExaminersPrimary: Powell, William A.Attorney, Agent or FirmInternational ClassesH01L 21/02 (20060101)H01L 21/311 (20060101) H01L 27/11 (20060101) AbstractA process for delineating a vertical resistor on a semiconductor device is disclosed. Resistive and diffusion barrier layers are deposited and then etched, first by dry plasma and then by wet bath. The two step etching allows complete removal of the deposited layers with minimal damage to exposed dielectric, silicide, polysilicon or doped regions on the semiconductor.Other References
|
| ||||||||||||||
