Two-wire bus-system comprising a clock wire and a data wire for interconnecting a number of stations
Patent 4689740 Issued on August 25, 1987. Estimated Expiration Date: 
August 25, 2004. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.
August 25, 2004. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.Patent References 3597549 3632881 3639694 3680056 3720790 3793488 3889236 3922486 Start and stop system Digital data communication adapter Patent #: 4168469 InventorsApplicationNo. 06/317693 filed on 11/02/1981US Classes:713/600, CLOCK CONTROL OF DATA PROCESSING SYSTEM, COMPONENT, OR DATA TRANSMISSION710/29, Flow controlling710/8Peripheral configurationExaminersPrimary: Shaw, Gareth D.Assistant: Eakman, Christina M. Attorney, Agent or FirmInternational ClassesG06F 13/42 (20060101)H04L 7/00 (20060101) AbstractA computer system comprises a number of stations which are interconnected by means of a clock bus wire (20) and a data bus wire (22) which both form a wired logic function of the signals generated thereon by the stations (32, 34). During the clock pulses, the signal on the data bus wire is stationary; it may change between the clock pulses. Start and stop conditions are formed by a signal combination between clock bus wire and data bus wire (60 and 62, respectively) which is not permissible in a data stream. If there is more than one master station so that a composite clock signal occurs on the clock bus wire, the clocks of the relevant master stations are each time resynchronized to the actual transitions in the composite clock signal. | |
