Method of making a planar MOS device in polysilicon

Patent 4688314 Issued on August 25, 1987. Estimated Expiration Date:

October 2, 2005. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.

Abstract Claims Description Full Text

Patent References

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Patent #: 4259680
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Method of fabricating n-type silicon regions and associated contacts Patent #: 4542580
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Inventors

Assignee

Advanced Micro Devices, Inc.

Application

No. 06/782842 filed on 10/02/1985

US Classes:

438/222, With epitaxial semiconductor layer formation257/E21.166, Conductive layer comprising semiconducting material (EPO)257/E21.507, Formation of contacts to semiconductor by use of metal layers separated by insulating layers, e.g., self-aligned contacts to source/drain or emitter/base (EPO)257/E21.616, MIS technology (EPO)257/E29.04, Of field-effect transistors with insulated gate (EPO)438/296, Dielectric isolation formed by grooving and refilling with dielectric material438/426, Recessed oxide laterally extending from groove438/586Combined with formation of ohmic contact to semiconductor region

Examiners

Primary: Hearn, Brian E.
Assistant: Bunch, William

Attorney, Agent or Firm

International Classes

H01L 21/02 (20060101)
H01L 29/02 (20060101)
H01L 21/285 (20060101)
H01L 21/60 (20060101)
H01L 29/08 (20060101)
H01L 21/70 (20060101)
H01L 21/8234 (20060101)

Abstract

A highly planarized integrated circuit structure having at least one MOS device is described as well as a method of making the structure. The structure comprises a substrate having a field oxide grown thereon with at least one portion defined therein for formation of a source/gate/drain region for an MOS device. All of the contacts of the device are formed using polysilicon which fills the defined portions in the field oxide resulting in the highly planarized structure.