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US Patent 4686759 - Method of manufacturing a semiconductor device
US Patent Issued on August 18, 1987
Estimated Patent Expiration Date:
September 12, 2004Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.
Estimated Patent Expiration Date:
September 12, 2004Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.AbstractMethod of manufacturing a semiconductor device and semiconductor device manufactured by the use of such a method.A method of contacting narrow regions, such as narrow polysilicon gates of a CCD, having widths of, for example, 4 μm. Upper layers, which are required for the CCD electrodes, are used as etching masks for contacts to the lower electrode layers. Two upper layers define two contact openings of 4 μm which are displaced both with respect to each other and with respect to the region to be contacted. Therefore it is possible to define a contact opening which is smaller than 4 μm and which is aligned accurately above the gate to be contacted.Other References
| InventorsApplicationNo. 06/649633 filed on 09/12/1984US Classes:438/587, Forming array of gate electrodes257/215, Charge transfer device257/734, COMBINED WITH ELECTRICAL CONTACT OR LEAD257/E21.457, With insulated gate (EPO)257/E29.138, For charge coupled devices (EPO)438/144, Charge transfer device (e.g., CCD, etc.)438/622Multiple metal levels, separated by insulating layer (i.e., multiple level metallization)ExaminersPrimary: Hearn, Brian E.Assistant: McAndrews, Kevin Attorney, Agent or FirmUS Patent References3681147, 4306353, Process for production of integrated MOS circuits with and without MNOS memory transistors in silicon-gate technologyIssued on: 12/22/1981 Inventor: Jacobs , et al.4380863Method of making double level polysilicon series transistor devices Issued on: 04/26/1983 Inventor: Rao International ClassesH01L 21/02 (20060101)H01L 29/40 (20060101) H01L 21/339 (20060101) H01L 29/423 (20060101) Foreign Application Priority Data1983-09-23 NL |
