MOS/CMOS memory cell
Patent 4679171 Issued on July 7, 1987. Estimated Expiration Date: 
February 7, 2005. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.
February 7, 2005. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.Patent ReferencesMetal-to-moat contacts in N-channel silicon gate integrated circuits using discrete second-level polycrystalline silicon Semiconductor memory device having stacked polycrystalline silicon layers Patent #: 4481524 InventorsAssigneeApplicationNo. 06/699051 filed on 02/07/1985US Classes:365/154, Flip-flop (electrical)257/390, Matrix or array of field effect transistors (e.g., array of FETs only some of which are completed, or structure for mask programmed read-only memory (ROM))257/659, WITH SHIELDING (E.G., ELECTRICAL OR MAGNETIC SHIELDING, OR FROM ELECTROMAGNETIC RADIATION OR CHARGED PARTICLES)257/69, Field effect transistor in single crystal material, complementary to that in non-single crystal, or recrystallized, material (e.g., CMOS)257/903, FET CONFIGURATION ADAPTED FOR USE AS STATIC MEMORY CELL257/E27.098, Static random access memory, SRAM, structure (EPO)257/E27.099, Load element being a MOSFET transistor (EPO)257/E27.101Load element being a resistor (EPO)ExaminersPrimary: Larkins, William D.Attorney, Agent or FirmInternational ClassH01L 27/11 (20060101)AbstractA memory array of four-IGFET-transistor cells arranged in rows and columns. The array uses two patterned metal layers and two patterned poly-silicon layers. For each column there is a pair of metal differential bit lines, formed on a first patterned metal layer. For each row there is a pair of split equipotential poly-silicon word lines and a parallel metal word line with connections to the split poly word lines at defined intervals. The parallel metal word line is on a second patterned metal layer distinct from the metal layer used for the bit lines. A grounded poly-silicon plate overlies the capacitive memory nodes of said array. The grounded poly-silicon plate is on a second patterned poly-silicon layer distinct from the poly-silicon layer used for the split word lines. The poly-silicon plate is connected to the circuit ground at defined intervals. Also, the poly-silicon plate provides alpha particle protection to the array and helps decouple the bit lines from the capacitive nodes of the array. | |
