Self-aligned inlay transistor with or without source and drain self-aligned metallization extensions
Patent 4677736 Issued on July 7, 1987. Estimated Expiration Date: 
April 17, 2006. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.
April 17, 2006. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.Patent ReferencesSelf-aligned field effect transistor process Method of fabricating a Schottky gate field effect transistor Field effect semiconductor devices and method of making same Fabrication technique for integrated circuits Process of making twin well VLSI CMOS Patent #: 4599789 InventorApplicationNo. 06/853108 filed on 04/17/1986US Classes:438/296, Dielectric isolation formed by grooving and refilling with dielectric material257/E21.346, Using mask (EPO)257/E21.432, With source and drain contacts formation strictly before final gate formation, e.g., contact first technology (EPO)257/E29.255, With field effect produced by insulated gate (EPO)438/297, Recessed oxide formed by localized oxidation (i.e., LOCOS)438/305, Plural doping steps438/945Special (e.g., metal, etc.)ExaminersPrimary: Hearn, Brian E.Assistant: Ham, Seungsook Attorney, Agent or FirmInternational ClassesH01L 21/336 (20060101)H01L 21/266 (20060101) H01L 21/02 (20060101) H01L 29/66 (20060101) H01L 29/78 (20060101) AbstractA self-aligned process is described for depositing gate electrode material in an inlay field effect transistor. The process particularly provides means for inclusion of lightly doped source and drain extensions to minimize high field effects in the channel region. The process described herein is also particularly useful for providing source and drain contact metal which also acts as an ion implantation mask layer during several of the process steps. The method described herein is usable in conventional VLSI fabrication production facilities.Other References
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