Simplified delay testing for LSI circuit faults
Patent 4672307 Issued on June 9, 1987. Estimated Expiration Date: 
December 20, 2005. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.
December 20, 2005. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.Patent References 3919637 Automatic testing of digital logic systems In-circuit digital tester Test system for LSI circuits resident on LSI chips Device for testing a circuit comprising sequential and combinatorial logic elements Patent #: 4435806 InventorsApplicationNo. 06/811349 filed on 12/20/1985US Classes:714/738Including test pattern generatorExaminersPrimary: Eisenzopf, Reinhard J.Assistant: Burn, B. Attorney, Agent or FirmInternational ClassesG06F 11/26 (20060101)G01R 31/30 (20060101) G01R 31/28 (20060101) G01R 31/3183 (20060101) G06F 11/27 (20060101) G06F 11/277 (20060101) G06F 11/273 (20060101) AbstractThorough delay testing of a combinational logic circuit is accomplished by changing only one input at a time (a single transition), and checking the output at a predetermined short time later, and arrangements are disclosed for systematically applying to the inputs of a combinational logic circuit all possible single transitions of the binary input signals. One economical test circuit uses a conventional binary counter and an associated ring counter to generate the test signals, in addition to input switching circuits or multiplexers for steering data to the logic to be tested and control circuitry to control the test process.Other References
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