Bit line gain circuit for read only memory
Patent 4661926 Issued on April 28, 1987. Estimated Expiration Date: 
November 20, 2004. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.
November 20, 2004. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.Patent ReferencesVirtual ground MOS EPROM or ROM matrix Signal comparison circuit Semiconductor memory circuit Patent #: 4388705 InventorAssigneeApplicationNo. 06/674103 filed on 11/20/1984US Classes:365/104, Transistors365/185.2, Reference signal (e.g., dummy cell)365/185.21, Sensing circuitry (e.g., current mirror)365/189.09Including reference or bias voltage generatorExaminersPrimary: Moffitt, James W.Assistant: Gossage, Glenn Attorney, Agent or FirmInternational ClassesG11C 16/08 (20060101)G11C 16/24 (20060101) G11C 16/26 (20060101) G11C 16/06 (20060101) G11C 17/14 (20060101) G11C 17/18 (20060101) AbstractA ROM memory circuit featuring a bit line gain circuit to the output thereof, effective for establishing isolation of bit and output lines, reduction of bit line voltage swing, VREF level tracking and bit line select circuitry performing a logical OR between two adjacent column select signals with no more than three transistors and effective for generation of a sinking current to maximize the slew rate of the output signal nodes.Other References
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