U.S. patents available from 1976 to present.
U.S. patent applications available from 2005 to present.

Self configuring computer network with automatic bus exchange of module identification numbers and processor assigned module numbers

Patent 4660141 Issued on April 21, 1987. Estimated Expiration Date: Icon_subject April 21, 2004. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.

Patent References

Module for coupling computer-processors
Patent #: 4253146
Issued on: 02/24/1981
Inventor: Bellamy ,   et al.

Common front-end control for a peripheral controller connected to a computer
Patent #: 4322792
Issued on: 03/30/1982
Inventor: Baun

Method and apparatus for controlling access of a network transmission bus between a plurality of spaced apart computer stations
Patent #: 4456956
Issued on: 06/26/1984
Inventor: El-Gohary ,   et al.

Memory system with automatic memory configuration
Patent #: 4507730
Issued on: 03/26/1985
Inventor: Johnson ,   et al.

Self-configuring digital processor system with global system
Patent #: 4562535
Issued on: 12/31/1985
Inventor: Vincent ,   et al.

Multiprocessor computer system Patent #: 4564900
Issued on: 01/14/1986
Inventor: Smitt

Inventors

Assignee

Application

No. 06/558779 filed on 12/06/1983

US Classes:

710/9, Address assignment340/825.52Addressing

Examiners

Primary: Williams, Archie E. Jr.

Attorney, Agent or Firm

International Classes

G06F 12/06 (20060101)
G06F 15/177 (20060101)
G06F 15/16 (20060101)

Abstract

In a computer network having a system bus, a system processor connected to the system bus, and a plurality of local processors each connected to a respective local bus each having a plurality of interface cards attached thereto, each interface card includes an identification ROM. Each interface card responds to an initial reset signal enabling that interface card to respond to the same initial address. Each local processor outputs that initial address. The closest interface card of each local bus responds by transmitting information from its identification ROM to the requesting local processor, which then assigns an address to the closest interface card, which then automatically sets circuitry that enables the next closest interface card to respond to the initial address. The procedure is repeated to assign unique addresses to all of the interface cards.

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