Memory sparing arrangement
Address mapping for memory
Defect tolerant memory
Memory system with selective assignment of spare locations
ApplicationNo. 06/687401 filed on 12/28/1984
US Classes:714/6, Redundant stored data accessed (e.g., duplicated data, error correction coded data, or other parity-type data)714/764Error correct and restore
ExaminersPrimary: Smith, Jerry
Assistant: Beausoliel, Robert W. Jr.
Attorney, Agent or Firm
International ClassesG06F 11/10 (20060101)
G11C 29/00 (20060101)
AbstractAn apparatus is disclosed which detects the existence of an error, in a computer system, corrects the error, and takes steps to ensure that the error will never again re-occur. The error resides in the integrity of data stored in a main memory. When the data is read from memory and found to be erroneous, the data is corrected and stored in a spare portion of a small alternate memory array. In addition, the identity of the corrected data is also stored in the alternate memory array. During a subsequent read of the data from the main memory, the alternate memory array is simultaneously consulted. The identity of the corrected data, stored in the alternate memory array, is compared with the incoming address, and the corrected data is read from the spare portion of the alternate memory array. As a result, the erroneous data is not reproduced during a subsequent read of the data from the main memory.