Digital radio paging communication system
Battery-saving arrangement for pagers
Selective call receiver having timed power supply
Battery saver for a paging receiver or the like _
Battery saver circuit for use with paging receiver
Energy conservation circuit for standby operation
Signal format detection circuit for digital radio paging receiver Patent #: 4554540
ApplicationNo. 06/700381 filed on 02/11/1985
US Classes:340/7.35, Address based340/7.38, Time based340/7.43, Particular message and address format (e.g., POCSAG, FLEX, etc.)455/343.3Based on identification
ExaminersPrimary: Yusko, Donald J.
Attorney, Agent or Firm
International ClassH04Q 7/18 (20060101)
Foreign Application Priority Data1984-02-14 JP
AbstractMethod and apparatus for use with a pager having a battery-saving function. The pager can receive calls addressed to it even when the pager fails to catch the preamble of the broadcast signal. The broadcast signal is received by a receiver which outputs a series of digital codes corresponding to the received signal. Changes in the level of the digital codes are detected by a change detection device which outputs pulses corresponding to the changes. A synchronization device receives the pulses and provides bit-synchronizing clock pulses therefrom. A counter then counts the number of clock pulses. The counter includes a gate signal generating device for dividing the clock pulses into first and second time-based segments. A comparison device then issues a command signal when the number of clock pulses in the first segment exceeds a first threshold value. The comparison device also compares the number of clock pulses counted in the second segment with a second threshold value when the command signal is issued. The comparison device then provides an output signal when both thresholds, respectively, are exceeded, indicating receipt of a true POCSAG signal. A battery-saving control device initiates the battery-saving function when either one of the first or second thresholds is not exceeded. When both thresholds are exceeded, an individual address code examining circuit examines the received signal for appropriate frame synchronization and individual address codes.