Computer memory system with integrated parallel shift circuits
Patent 4644503 Issued on February 17, 1987. Estimated Expiration Date: 
February 17, 2004. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.
February 17, 2004. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.Patent References 3893088 Apparatus for image manipulation Parallel access memory system Image rotation apparatus Code converter circuitry system for selectively rotating a video display picture Row address linking control system for video display terminal Apparatus for parallel processing of local image data Patent #: 4550437 InventorsApplicationNo. 06/567215 filed on 12/30/1983US Classes:365/189.12, With shift register345/554, Multi-port memory365/230.03, Plural blocks or banks365/238, Cartesian memories365/238.5Byte or page addressingExaminersPrimary: Fears, Terrell W.Attorney, Agent or FirmInternational ClassesG11C 7/10 (20060101)G09G 1/02 (20060101) AbstractThe system includes a plurality of memory units each for storing a plurality of independently addressable binary bits. The units operate together in response to each common bit address to supply a bit from each unit to form an array of bits for a discrete section of a larger array. The units are interconnected through common interconnection buses and selectively actuable input and output gate connections to those buses to provide for selective shifting of bits between units to change the bit array.Other References
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