Distributed pattern generator
January 27, 2004. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.Patent References Re31056 3772595 Test generator for random access memories Test pattern generating apparatus Function test evaluation apparatus for evaluating a function test of a logic circuit Semiconductor memory test equipment Memory address selector Semiconductor memory test pattern generating apparatus Test vector indexing method and apparatus Method and system for selectively loading test data into test data storage means of automatic digital test equipment InventorsApplicationNo. 06/564853 filed on 12/19/1983US Classes:714/743AddressingExaminersPrimary: Atkinson, Charles E.Attorney, Agent or FirmInternational ClassesG01R 31/28 (20060101)G01R 31/319 (20060101) G01R 31/3193 (20060101) G11C 29/36 (20060101) G11C 29/04 (20060101) G11C 29/56 (20060101) AbstractAn array testing apparatus includes a plurality of pin pattern generators for individually generating serial bit sequences required at each pin of a device under test during the testing operation. The individual pin pattern generators receive starting addresses from one or more programmable controllers and each pin pattern generator then performs a subroutine to repeat basic patterns or combinations of basic patterns as necessary. Both the pin pattern generators and the programmable controllers may include loop logic for obtaining the desired repetition sequences. | |
