On chip test system for configurable gate arrays
June 26, 2005. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.Patent ReferencesChip and wafer configuration and testing method for large-scale-integrated circuits Test system for LSI circuits resident on LSI chips Method of testing a logic system and a logic system for putting the method into practice Self verifying logic system Method and arrangement for an operational check of a programmable logic array LSI self-test method Random testing using scan path technique Logic circuit test system Patent #: 4584683 InventorsAssigneeApplicationNo. 06/748885 filed on 06/26/1985US Classes:714/732, Signature analysis714/733, Built-in testing circuit (BILBO)714/738Including test pattern generatorExaminersPrimary: Fleming, Michael R.Attorney, Agent or FirmInternational ClassesG01R 31/3185 (20060101)G01R 31/28 (20060101) AbstractAn on chip test system for arrays is provided that includes self test and maintenance operation while allowing for both synchronous and pipeline modes of normal operation. The system is integrated on a chip that includes a plurality of inputs and a plurality of outputs. A plurality of gates are coupled between the plurality of inputs and outputs wherein input signals may be transmitted asynchronously to the gates and output signals may be transmitted asynchronously to the outputs. An input shift register is coupled between each of the inputs and the gates for synchronously transmitting input signals, and an output shift register is coupled between the gates and each of the outputs for synchronously transmitting output signals. A control logic circuit is coupled to the plurality of gates, the input shift registers, and the output shift registers for selecting the systems mode of operation. A comparator circuit is coupled to the output shift registers for comparing said output signals with expected signals.Other References
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