Method for the production of mask patterns for integrated semiconductor circuits
Macro assembler process for automated circuit design
Automatic layout program for hybrid microcircuits (HYPAR) Patent #: 4500963
ApplicationNo. 06/554855 filed on 11/23/1983
US Classes:716/9Detailed placement (i.e., iterative improvement)
ExaminersPrimary: Gruber, Felix D.
Assistant: Cosimano, Edward R.
Attorney, Agent or Firm
International ClassG06F 17/50 (20060101)
AbstractA method for placing a plurality of different size electronic elements having predetermined interconnection requirements thereamong, on a next level electronic package having an array of element placement positions thereon determines optimum placement in a three pass process. In the first pass, all of the elements are treated as if they are the same size, defined as a unit size, and are assigned to element positions on a unit size next level package, then their placement is optimized. These unit size elements are then replaced by macro size elements, which are approximately the actual size of the corresponding electronic elements. The macro size elements are then rearranged for optimal placement on a macro model image, taking their sizes and shapes into account. Finally, the macro size elements are replaced by actual size elements which are placed on an actual size next level package in element positions, and their placement is again optimized. By optimizing element placement in a three pass process, i.e., unit, macro and actual size, a more efficient placement process is obtained because the element placement program need not take all of the dimensional characteristics of the elements into account at once.