Watchdog timer
Patent 4627060 Issued on December 2, 1986. Estimated Expiration Date: 
November 29, 2004. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.
November 29, 2004. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.Patent ReferencesProtection system for electrostatographic machines Supervisory control apparatus Microprocessor-based load management terminal with reset Automatic processor restart circuit One-chip semiconductor device incorporating a power-supply-potential detecting circuit with reset function Patent #: 4551841 InventorsAssigneeApplicationNo. 06/676130 filed on 11/29/1984US Classes:714/36, Test sequence at power-up or initialization714/55, Timing error (e.g., watchdog timer time-out)714/815Time delay/interval monitoredExaminersPrimary: Atkinson, Charles E.Attorney, Agent or FirmInternational ClassesG06F 1/24 (20060101)G06F 11/00 (20060101) G06F 9/48 (20060101) G06F 9/46 (20060101) AbstractA self-checking timer usable with a host system includes a clock and a plurality of interconnected counters. During a power-up phase the timer generates a system reset signal and counts the counters in a predetermined sequence. A flip-flop is set and reset during the power-up phase and inhibits generation of the system reset signal. During a normal operating phase, the timer generates a test signal that must be responded to by the host system to continuously inhibit generation of the system reset signal. | |
