Glitch lockout circuit for memory array
December 2, 2003. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.Patent References 3778784 Memory circuit Memory array Clock generator for semiconductor memory Semiconductor memory device Column decoder discharge for semiconductor memory Dummy columns for reducing pattern sensitivity in MOS/LSI dynamic RAM Dummy cell arrangement for an MOS memory Semiconductor integrated circuit device Random access semiconductor memory device using MOS transistors InventorsAssigneeApplicationNo. 06/554914 filed on 11/25/1983US Classes:365/203, Precharge365/210, Reference or dummy element365/233Sync/clockingExaminersPrimary: Moffitt, James W.Assistant: Gossage, Glenn Attorney, Agent or FirmInternational ClassesG11C 11/419 (20060101)G11C 7/00 (20060101) G11C 7/14 (20060101) G11C 7/24 (20060101) G11C 7/12 (20060101) G11C 11/409 (20060101) G11C 11/4094 (20060101) AbstractThe present invention relates to a glitch lockout circuit for a static random access memory (RAM) which prevents the writing or reading of incorrect data when a system clock is switched from a standard clock source to an alternate clock source. A dummy bit line is added to the memory arrangement which is always precharged during a first clock phase and discharged during a second clock phase. The state of the dummy bit line is latched with the first clock phase and is fed back to the clock generator to control the initiation of the second clock phase. Thus, if the dummy bit line stays low, the second clock phase will stay low and none of the RAM cells will be accessed.Other References
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