U.S. patents available from 1976 to present.
U.S. patent applications available from 2005 to present.

Linked component extraction circuit for image processor

Patent 4624013 Issued on November 18, 1986. Estimated Expiration Date: Icon_subject March 27, 2005. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.

Patent References

Image analysis system and method for minimizing paralysis angle
Patent #: 4069411
Issued on: 01/17/1978
Inventor: Morton

System for extracting shape features from an image
Patent #: 4183013
Issued on: 01/08/1980
Inventor: Agrawala ,   et al.

Multilevel processing of image signals Patent #: 4189711
Issued on: 02/19/1980
Inventor: Frank

Inventor

Application

No. 06/716459 filed on 03/27/1985

US Classes:

382/180, Region labeling (e.g., page description language)382/204Topological properties (e.g., number of holes in a pattern, connectivity, etc.)

Examiners

Primary: Boudreau, Leo H.

Attorney, Agent or Firm

International Classes

G06T 7/00 (20060101)
G06K 9/46 (20060101)

Foreign Application Priority Data

1984-03-31 JP

Abstract

A linked component extraction circuit has a FIFO memory for sequentially storing information pairs each consisting of two label values which are generated from a linked component detector and which have a linking relationship therebetween, and for reading out a currently oldest information pair when the FIFO memory is subjected to read access. A read/write unit reads out storage data (i.e., the label value) from a memory area of the table memory at an address accessed by the first label value of the information pair or the readout output data and writes the second label value of the information pair read out from the FIFO memory at the same address. The storage data read out from the table memory at the address accessed by the first label value is compared with the first label value by a comparator to generate a coincidence or noncoincidence signal. When noncoincidence is detected by the comparator, the storage data is used as the address for read/write operation of the read/write unit until the next coincidence signal is generated by the comparator. When coincidence is detected by the comparator, the next information pair is read out from the FIFO memory, and the above operation is repeated.

PatentsPlus Images
Enhanced PDF formats
loading...
PatentsPlus: add to cart
PatentsPlus: add to cartSearch-enhanced full patent PDF image
$9.95more info
PatentsPlus: add to cart
PatentsPlus: add to cartIntelligent turbocharged patent PDFs with marked up images
$16.95more info
 
Sign InRegister
Username  
Password   
forgot password?