Method of making junction field effect transistor of static induction type
April 30, 2005. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.Patent ReferencesPower static induction transistor fabrication Semiconductor device design and process Non-epitaxial static induction transistor processing Etched-source static induction transistor Etched-source static induction transistor Self-aligned high-frequency static induction transistor Recessed gate static induction transistor fabrication Method of fabrication of a low capacitance self-aligned semiconductor electrode structure Method of making self-aligned high-frequency static induction transistor Method of fabricating submicron silicon structures such as permeable base transistors InventorsAssigneeApplicationNo. 06/729025 filed on 04/30/1985US Classes:438/193, Multiple parallel current paths (e.g., grid gate, etc.)257/264, Enhancement mode or with high resistivity channel (e.g., doping of 10 15 cm -3 or less)257/266, With multiple parallel current paths (e.g., grid gate)257/287, With multiple channels or channel segments connected in parallel, or with channel much wider than length between source and drain (e.g., power JFET)257/E21.401, Using static field induced region, e.g., SIT, PBT (EPO)257/E29.243Using static field induced region (e.g., SIT, PBT) (EPO)ExaminersPrimary: Roy, UpendraAttorney, Agent or FirmInternational ClassesH01L 21/335 (20060101)H01L 29/66 (20060101) H01L 21/02 (20060101) H01L 29/772 (20060101) AbstractJunction field effect transistor, specifically a static induction transistor, and method of fabricating. An epitaxial layer of high resistivity N-type silicon is grown on a substrate of low resistivity silicon. The surface of the epitaxial layer is coated with silicon nitride, portions of the silicon nitride are removed, and the silicon is etched to form parallel grooves with interposed ridges of silicon. A layer of silicon nitride is applied and then removed except from the side walls of the grooves. Exposed silicon at the bottoms of the grooves is converted to silicon dioxide to build up layers of silicon dioxide in the grooves. The remaining silicon nitride is removed. P-type conductivity imparting material is ion implanted into alternate (gate) ridges and diffused to form gate regions which extend laterally beneath the silicon dioxide in the adjacent grooves. N-type conductivity imparting material is ion implanted in the top of the intervening (source) ridges. Metal contacts are applied to the gate ridges, the source ridges, and the substrate. | |
