Interface circuit for interconnecting peripherals to an information processing device
Patent 4608504 Issued on August 26, 1986. Estimated Expiration Date: 
August 26, 2003. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.
August 26, 2003. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.Patent ReferencesMultiprocessor system Tri-state CMOS driver having reduced gate delay Patent #: 4465945 InventorApplicationNo. 06/479433 filed on 03/28/1983US Classes:326/86, Bus driving326/10, Redundant326/114, Wired logic (e.g., wired-OR, wired-AND, dotted logic, etc.)326/125, Wired logic or open collector logic (e.g., wired-OR, wired-AND, dotted logic, etc.)326/14, Fail-safe326/30, Bus or line termination (e.g., clamping, impedance matching, etc.)326/56, TRI-STATE (I.E., HIGH IMPEDANCE AS THIRD STATE)326/83, Field-effect transistor327/530With specific source of supply or bias voltageExaminersPrimary: Miller, Stanley D.Assistant: Hudspeth, D. R. Attorney, Agent or FirmInternational ClassesG06F 1/26 (20060101)G06F 13/40 (20060101) Foreign Application Priority Data1983-01-20 JPAbstractAn interface circuit for an information processing device comprises a plurality of buffer circuits each formed of a plurality of C-MOS tri-state buffers. The buffers are provided for communicating between the devices and an interface line which includes a power supply line and a signal line. Each buffer is powered from its specific power source and if this specific power source is inoperative, from the remaining power sources other than its specific power source. | |
