Digital communication system
High speed data switching node
Four-wire speed independent arbiter switch for digital communication networks
Computer-communications concentrator for transmission and switching of packetized data
Transparent intelligent network for data and voice
Local area communication network
Bi-directional token flow system Patent #: 4464749
ApplicationNo. 06/560732 filed on 12/12/1983
US Classes:370/417, Having output queuing only370/395.7, Having detail of switch memory reading/writing370/422Centralized switching
ExaminersPrimary: Olms, Douglas W.
Assistant: Kuntz, Curtis
International ClassesH04J 3/06 (20060101)
H04L 12/56 (20060101)
Foreign Application Priority Data1982-12-29 FR
AbstractThe system switches data packets, with headers, from input junctions to output junctions. The series incoming packets are converted into parallel packets. The headers of each incoming packet and the identity of the involved input junction are transferred to the address inputs of a control memory. The control memory supplies a new header which is assigned to the incoming packet, in replacement of the original header, in order to form the parallel outgoing packet with the remaining part of the incoming packet. A buffer memory is cyclically enabled for writing, in order to store the outgoing packets. Each parallel packet read out of the buffer memory is converted into a series packet. Queues store the addresses of a packet in the buffer memory, and are selectively enabled for writing, depending on information from the control memory. Each queue is assigned to an output junction. Responsive to a signal for indicating that one of the output junctions is enabled, the address contained in the corresponding queue is read, in order to find the output packet which is to be transferred to the outgoing junction in the buffer memory.