PROM electrically written by solid phase epitaxy
Thin film memory device employing amorphous semiconductor materials
Amorphous semiconductors equivalent to crystalline semiconductors
Method for optimizing photoresponsive amorphous alloys and devices Patent #: 4342044
ApplicationNo. 06/649205 filed on 09/10/1984
US Classes:365/163, Amorphous (electrical)257/300, Capacitor coupled to, or forms gate of, insulated gate field effect transistor (e.g., non-destructive readout dynamic memory cell structure)257/311, Storage Node isolated by dielectric from semiconductor substrate257/530, Anti-fuse257/E27.004, Including solid state component for rectifying, amplifying, or switching without a potential barrier or surface barrier (EPO)257/E29.17, Memory effect devices (EPO)257/E29.327, Diode (EPO)257/E29.33, Hi-lo semiconductor device (e.g., memory device) (EPO)365/103Semiconductive
ExaminersPrimary: Fears, Terrell W.
Attorney, Agent or Firm
International ClassesH01L 29/68 (20060101)
H01L 27/24 (20060101)
H01L 29/66 (20060101)
H01L 29/861 (20060101)
AbstractA programmable cell for use in programmable electronic arrays such as PROM devices, logic arrays, gate arrays and die interconnect arrays. The cells have a highly non-conductive state settable and substantially non-resettable into a highly conductive state. The cells have a resistance of 10,000 ohms or more in the non-conductive state which are settable into the conductive state by a threshold voltage of 20 volts or less, a current of 25 milliamps or less, for 1000 microseconds or less. The cells in the conductive state have a resistance of 500 ohms or less. The cells have a maximum permittable processing temperature of 200° centigrade or more and a storage temperature of 175° centigrade or more. The cells can be formed from chalcogenide elements, such as germanium tellurium and selenium or combination thereof. The cells also can be formed from tetrahedral elements, such as silicon, germanium and carbon or combinations thereof.Each cell in an array is a thin film deposited cell and includes an isolating device which can be a bipolar or MOS device or can be a thin film diode or transistor. The associated addressing circuitry also can be conventional bipolar or MOS devices or thin film deposited devices. The cells have a cell area of less than one square mil to provide a high cell packing density.
Field of SearchAmorphous (electrical)