U.S. patents available from 1976 to present.
U.S. patent applications available from 2005 to present.

Method of making semiconductor integrated circuits having backside gettered with phosphorus

Patent 4589928 Issued on May 20, 1986. Estimated Expiration Date: Icon_subject August 21, 2004. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.

Patent References

3740835

3811975

Elimination of stacking faults in silicon devices: a gettering process
Patent #: 3997368
Issued on: 12/14/1976
Inventor: Petroff ,   et al.

Impact sound stressing for semiconductor devices
Patent #: 4018626
Issued on: 04/19/1977
Inventor: Schwuttke ,   et al.

Method of gettering using backside polycrystalline silicon
Patent #: 4053335
Issued on: 10/11/1977
Inventor: Hu

Reliable metal-to-junction contacts in large-scale-integrated devices
Patent #: 4114256
Issued on: 09/19/1978
Inventor: Thibault ,   et al.

Manufacture of semiconductor devices in which a doping impurity is diffused from a polycrystalline semiconductor layer into an underlying monocrystalline semiconductor material, and semiconductor devices thus manufactured
Patent #: 4124934
Issued on: 11/14/1978
Inventor: De Brebisson

Gettering semiconductor wafers with a high energy laser beam
Patent #: 4131487
Issued on: 12/26/1978
Inventor: Pearce ,   et al.

Method of manufacturing Si gate MOS integrated circuit
Patent #: 4151631
Issued on: 05/01/1979
Inventor: Klein

Structure for shallow junction MOS circuits
Patent #: 4291322
Issued on: 09/22/1981
Inventor: Clemens ,   et al.

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Inventors

Assignee

Application

No. 06/642932 filed on 08/21/1984

US Classes:

438/143, Gettering of semiconductor substrate257/E21.274, Deposition from gas or vapor (EPO)257/E21.318, Of silicon body, e.g., for gettering (EPO)257/E21.585, Filling of holes, grooves, vias or trenches with conductive material (EPO)257/E21.627, Interconnection or wiring or contact manufacturing related aspects (EPO)438/476By layers which are coated, contacted, or diffused

Examiners

Primary: Roy, Upendra

Attorney, Agent or Firm

International Classes

H01L 21/768 (20060101)
H01L 21/02 (20060101)
H01L 21/70 (20060101)
H01L 21/322 (20060101)
H01L 21/316 (20060101)
H01L 21/8234 (20060101)

Abstract

For achieving dense packing of MOS transistors at the top surface of a silicon semiconductor body, second level metallization including arsenic doped polysilicon contacts are used in conjunction with a phosphorus gettering step at a time when the top surface is sealed against the introduction of phosphorus by an undoped sacrificial glass layer, i.e., which is essentially free of phosphorus. The second level metallization is thereafter completed by coating the polysilicon with a high conductivity metal, such as aluminum. During the gettering, the polysilicon contacts are insulated from the first level metallization by a planarized glass layer doped with phosphorus to a concentration below the saturation level of phosphorus in the glass.

Other References

  • Pak et al. IBM-TDB, 18 (1975) 2183
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