U.S. patents available from 1976 to present.
U.S. patent applications available from 2005 to present.

Differential phase shift keying receiver

Patent 4575684 Issued on March 11, 1986. Estimated Expiration Date: Icon_subject February 22, 2005. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.

Patent References

3401339

3479598

3551814

3739277

3746995

Digital demodulator for phase-modulated waveforms
Patent #: 3938052
Issued on: 02/10/1976
Inventor: Glasson ,   et al.

Method and apparatus for decoding diphase signals
Patent #: 3982195
Issued on: 09/21/1976
Inventor: Turner

Digital demodulator for differentially encoded phase-shift-keyed data
Patent #: 3997847
Issued on: 12/14/1976
Inventor: Tong

Method and apparatus for a PSK signal detector
Patent #: 4233565
Issued on: 11/11/1980
Inventor: Chmura

Digital coherent phase demodulator
Patent #: 4246654
Issued on: 01/20/1981
Inventor: Malm

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Inventor

Assignee

Application

No. 06/704433 filed on 02/22/1985

US Classes:

329/307, Including phase or frequency locked loop329/310, Including logic element (e.g., logic gate or flip-flop)375/330Differential (diphase)

Examiners

Primary: LaRoche, Eugene R.
Assistant: Lee, James C.

Attorney, Agent or Firm

International Classes

H04L 27/227 (20060101)
H04L 27/18 (20060101)

Abstract

A receiver for demodulating differential phase shift keying data, the data having bit values dependent upon whether the phase of a carrier is inverted or not inverted during a bit interval, the receiver having a phase locked loop oscillator for locking up with the phase of the carrier, a phase detector for sensing differences in phases between the oscillator signal and the incoming data, an oscillator controller for controlling the output phase of the oscillator in response to the phase detector, a phase sense detector which detects whether or not the carrier has been inverted, a data clock responsive to the oscillator and to the phase sense detector for providing a data clock signal defining a bit interval, and a bit detector responsive to the phase sense detector, the data clock and the oscillator for integrating the incoming data.

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